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Pure Storage Certified FlashArray Implementation Specialist Sample Questions (Q181-Q186):

NEW QUESTION # 181
What is the default FlashArray//XLR5 - FC configuration shipped for new installs?

A. 4-port 32G FC card with 32G optics installed in PCIe Slot 1; 2-Port 32G FC card with 32G optics installed in PCIe slot 3; DirectCompress Accelerator installed in PCIe slot 8
B. 4-port 32G FC card with 32G optics installed in PCIe slot 3; 2-Port 32G FC card with 32G optics installed in PCIe slot 5; DirectCompress Accelerator installed in PCIe slot 6
C. 4-Port 32G FC card with 32G optics installed in PCIe slot 4; 2-Port 32G FC card with 32G optics installed in PCIe slot 3; DirectCompress Accelerator installed in PCIe slot 5

Answer: B

Explanation:
The FlashArray//XL series has a specific, validated slot population rule for its PCIe cards to ensure optimal performance and thermal management. For a standard Fibre Channel (FC) configuration on a FlashArray//XLR5, the factory default shipment includes a specific arrangement of host I/O cards and offload engines.
The correct default configuration is:
PCIe Slot 3: 4-Port 32Gb FC card.
PCIe Slot 5: 2-Port 32Gb FC card.
PCIe Slot 6: DirectCompress Accelerator (DCA).
This layout (Option B) adheres to the //XL's architecture where specific slots are prioritized for frontend host I/O (like slots 3 and 5) and others for offload functions or backend connectivity. Implementation Engineers must verify cards are in these exact slots during the visual inspection. If cards are moved to incorrect slots (like slot 1 or 4 for primary FC in this specific config), the array may not boot or may fail to initialize the FC services correctly due to BIOS enumeration orders.
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NEW QUESTION # 182
Where can the NVRAM on a FlashArray//E be located?

A. Distributed across DFMDs
B. Within the dedicated NVRAMS
C. Distributed across DFMes

Answer: A

Explanation:
The FlashArray//E (and the //XR4/R5 family) utilizes a modern architecture that moves away from the dedicated NVRAM modules found in legacy generations (like the //XR2 and //XR3). In those older systems, NVRAM was housed in specific PCIe cards plugged into the chassis.
In the FlashArray//E architecture, the Non-Volatile RAM (write buffer) functionality is Distributed directly onto the storage media itself. These specialized drives are called DFMDs (DirectFlash Modules with Distributed NVRAM).
By integrating the NVRAM into the DFMs, the array scales its write buffer cache linearly with capacity and removes the bottleneck of fixed NVRAM slots in the chassis. This allows for higher density and simplified hardware designs. During installation or inventory, engineers must distinguish between standard DFMs (which store data only) and DFMDs (which store data and act as the write cache), ensuring the correct number of DFMDs are present to form the system quorum.
=========

NEW QUESTION # 183
What are the interface names for a 4-port FC card in slot 1 in an XR2/3 array?

A. FC0, FC1, FC2, and FC3
B. FC5, FC6, FC7, and FC8
C. FC4, FC5, FC6, and FC7

Answer: C

Explanation:
On a FlashArray//XR2 or //XR3 equipped with a 4-port Fibre Channel card in Slot 1, the interfaces are named FC4, FC5, FC6, and FC7.
The port enumeration logic on FlashArray controllers follows a sequential order based on the PCIe slot number:
Slot 0: This is the first PCIe slot. If a 4-port card is installed here (which is typical for the primary host I/O card), it claims the first block of names: FC0, FC1, FC2, and FC3.
Slot 1: This is the second PCIe slot. A 4-port card installed here continues the sequence immediately after Slot 0. Therefore, it claims FC4, FC5, FC6, and FC7.
Slot 2: Any card here would start at FC8 (if the previous slots are 4-port).
Option A describes the mapping for Slot 0. Option C describes a non-standard mapping that skips integers or assumes a different starting point. Correctly identifying these interface names is crucial for zoning (SAN configuration) and creating the correct host port definitions during the implementation.

NEW QUESTION # 184
Which cards are required to connect a DirectFlash Shelf to an FlashArray//XLR5?

A. 2-Port 50GbE
B. 2-port 200GbE Ethernet/RoCE
C. 2-Port 100GbE iSCSI/RoCE

Answer: C

Explanation:
The FlashArray//XL series (specifically the //XLR5 in this context) utilizes a 100 Gigabit Ethernet-based back-end fabric to communicate with DirectFlash Shelves (DFS). This connection relies on the RoCE (RDMA over Converged Ethernet) protocol to ensure low-latency access to the external NVMe modules.
The specific PCIe interface card validated for this connectivity is often labeled in the Bill of Materials (BOM) or configuration guides as the 2-Port 100GbE iSCSI/RoCE card (or simply the 100GbE Ethernet/RoCE card depending on the specific firmware/labeling revision). Crucially, it must be a 100GbE capability card.
The //XL platform standardized on 100GbE for its shelf interconnects, moving away from the 50GbE used in some previous generations of the //X series. The 200GbE cards are typically reserved for high-speed host connectivity or clustering, not the standard shelf loop. Therefore, ensuring the BOM includes the correct 100GbE RoCE-capable cards is essential for successful shelf detection and operation during installation.

NEW QUESTION # 185
An Implementation Engineer is installing the first DirectFlash Shelf (DFS) on a FlashArray//XR4 controller. Which ports should the Implementation Engineer use for the connection?

A. ETH 0/1
B. ETH 18/19
C. ETH 10/11

Answer: B

Explanation:
The FlashArray//XR4 utilizes onboard 100GbE RoCE (RDMA over Converged Ethernet) ports for connecting to the first loop of DirectFlash Shelves, removing the need for dedicated PCIe add-in cards for the base configuration. The port mapping for these onboard backend ports differs from previous generations.
On the //XR4 controller chassis, the specific Ethernet interfaces designated for the first DirectFlash Shelf loop are typically the high-numbered onboard ports. In this specific exam context and hardware revision, ETH 18 and ETH 19 are identified as the correct primary backend connectivity ports .
Implementation Engineers must connect the QSFP28 cables from the "uplink" ports on the first shelf (IOM0 and IOM1) to ETH18 and ETH19 on the controllers (CT0 and CT1) respectively. Using incorrect ports (like ETH0/1, which are management) would result in the shelf not being detected by the storage fabric.
=========

NEW QUESTION # 186
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Pure Storage Certified FlashArray Implementation Specialist Sample Questions (Q181-Q186):

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